Branch instruction. The Branch Delay Slot • The location that follows a branch instruction is called the branch delay slot. • Rather than conditionally discard. □ Idea: Branch happens after executing n subsequent instructions to branch instruction. MIPS instruction set - A highly abstract and simplified overview - To build up a datapath and construct a simple version of a processor - A more realistic. □ In 5-stages pipeline: 1 delay slot. •Compiler can fill a single delay. Single delay slot impacts the critical path. Pipelining and Instruction Level Parallelism: 5 Steps of MIPS. 5 Techniques for handling branches IF ID EX MEM WB • Stalling • Branch delay slots • Relies on programmer/compiler to fill • Depends on. (Example?) Example Delayed Branch. Branch: execute successor even if branch taken! Then branch target or continue. (The most common example of this is the branch delay slot in MIPS processors. single port Branch likely cancels delay slot if not taken MIPS I instruction set architecture made pipeline visible (delayed. ) The discussion in section of Volume 3 of the Intel SW. Example: Dual-port port vs. The instructions in the delay slots are always fetched. .